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szz

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    Tiro
  1. Hey; commented out the line 54 and the for loop at line 648, now the game launch properly!! Really appreciated! If I can do anything more count on me! P.D: If I experiment anything weird while playing I'll post it here! Thanks!!
  2. Hey! applied your patch and recompiled, Here you have your registers: TIMER| InitVfs: 644.914 us Writing the mainlog at /home/szz/.config/0ad/logs/mainlog.html TIMER| CONFIG_Init: 1.90555 ms Sound: AlcInit success, using OpenAL Soft TIMER| shutdown ConfigDB: 5.308 us TIMER| resource modules: 3.19084 ms TIMER TOTALS (9 clients) ----------------------------------------------------- tc_pool_alloc: 0 c (0x) tc_png_decode: 0 c (0x) tc_dds_transform: 0 c (0x) tc_transform: 0 c (0x) tc_plain_transform: 0 c (0x) tc_ShaderGLSLLink: 0 c (0x) tc_ShaderGLSLCompile: 0 c (0x) tc_ShaderValidation: 0 c (0x) xml_validation: 0 c (0x) ----------------------------------------------------- TIMER| shutdown misc: 267.632 us TIMER| InitVfs: 762.737 us Writing the mainlog at /home/szz/.config/0ad/logs/mainlog.html TIMER| CONFIG_Init: 2.64747 ms Sound: AlcInit success, using OpenAL Soft eax: 0x36006400, ebx: 0x56006400, ecx: 0x2006140, edx: 0x100A140 cache.cpp(54): Assertion failed: "tlb.Validate()" Assertion failed: "tlb.Validate()" Location: cache.cpp:54 (AddTLB) Call stack: (0x5605aee77fbe) binaries/system/pyrogenesis(+0x5fffbe) [0x5605aee77fbe] (0x5605aee239f1) binaries/system/pyrogenesis(+0x5ab9f1) [0x5605aee239f1] (0x5605aee24ee8) binaries/system/pyrogenesis(+0x5acee8) [0x5605aee24ee8] (0x5605aee253e8) binaries/system/pyrogenesis(+0x5ad3e8) [0x5605aee253e8] (0x5605aee704be) binaries/system/pyrogenesis(+0x5f84be) [0x5605aee704be] (0x5605aee707e3) binaries/system/pyrogenesis(+0x5f87e3) [0x5605aee707e3] (0x5605aee709dc) binaries/system/pyrogenesis(+0x5f89dc) [0x5605aee709dc] (0x5605aee70e85) binaries/system/pyrogenesis(+0x5f8e85) [0x5605aee70e85] (0x5605aeea6263) binaries/system/pyrogenesis(+0x62e263) [0x5605aeea6263] (0x5605aee716ce) binaries/system/pyrogenesis(+0x5f96ce) [0x5605aee716ce] (0x5605aee7255a) binaries/system/pyrogenesis(+0x5fa55a) [0x5605aee7255a] (0x5605aeea6263) binaries/system/pyrogenesis(+0x62e263) [0x5605aeea6263] (0x5605aee7213a) binaries/system/pyrogenesis(+0x5fa13a) [0x5605aee7213a] (0x5605aeb21c8f) binaries/system/pyrogenesis(+0x2a9c8f) [0x5605aeb21c8f] (0x5605aeb189f9) binaries/system/pyrogenesis(+0x2a09f9) [0x5605aeb189f9] (0x5605ae92bc51) binaries/system/pyrogenesis(+0xb3c51) [0x5605ae92bc51] errno = 0 (Invalid alignment) OS error = ? (C)ontinue, (S)uppress, (B)reak, Launch (D)ebugger, or (E)xit? Thanks for your attention!
  3. Hey! there you go: cpuid -1: (I guess all the processors are identical and there are a few ...) CPU: vendor_id = "AuthenticAMD" version information (1/eax): processor type = primary processor (0) family = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15) model = 0x1 (1) stepping id = 0x1 (1) extended family = 0x8 (8) extended model = 0x0 (0) (simple synth) = AMD Ryzen (Summit Ridge B1) [Zen], 14nm miscellaneous (1/ebx): process local APIC physical ID = 0xc (12) cpu count = 0x20 (32) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true VME: virtual-8086 mode enhancement = true DE: debugging extensions = true PSE: page size extensions = true TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true MCE: machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true MTRR: memory type range registers = true PTE global bit = true MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true PSE-36: page size extension = true PSN: processor serial number = false CLFLUSH instruction = true DS: debug store = false ACPI: thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true SS: self snoop = false hyper-threading / multi-core supported = true TM: therm. monitor = false IA64 = false PBE: pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true DTES64: 64-bit debug store = false MONITOR/MWAIT = true CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false TM2: thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false PDCM: perfmon and debug = false PCID: process context identifiers = false DCA: direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true x2APIC: extended xAPIC support = false MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = false AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = false cache and TLB information (2): processor serial number: 0080-0F11-0000-0000-0000-0000 MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x40 (64) largest monitor-line size (bytes) = 0x40 (64) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x0 (0) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false Intel Turbo Boost Max Technology 3.0 = false HWP capabilities = false HWP PECI override = false flexible HWP = false IA32_HWP_REQUEST MSR fast access mode = false ignoring idle logical processor HWP req = false digital thermometer thresholds = 0x0 (0) hardware coordination feedback = true ACNT2 available = false performance-energy bias capability = false extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI1 instructions = true HLE hardware lock elision = false AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = false INVPCID instruction = false RTM: restricted transactional memory = false RDT-M: Intel RDT monitoring = false deprecated FPU CS/DS = false MPX: intel memory protection extensions = false RDT-A: Intel RDT allocation = false AVX512F: AVX-512 foundation instructions = false AVX512DQ: double & quadword instructions = false RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: fused multiply add = false PCOMMIT instruction = false CLFLUSHOPT instruction = true CLWB instruction = false Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = false SHA instructions = true AVX512BW: byte & word instructions = false AVX512VL: vector length = false PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = false UMIP: user-mode instruction prevention = false PKU protection keys for user-mode = false OSPKE CR4.PKE and RDPKRU/WRPKRU = false WAITPKG instructions = false AVX512_VBMI2 = false CET_SS: CET shadow stack = false GFNI: Galois Field New Instructions = false VAES instructions = false VPCLMULQDQ instruction = false AVX512_VNNI = false AVX512_BITALG: bit count/shiffle = false AVX512: VPOPCNTDQ instruction = false 5-level paging = false BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor D supported = false CLDEMOTE supports cache line demote = false MOVDIRI instruction = false MOVDIR64B intruction = false SGX_LC: SGX launch config supported = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false fast short REP MOV = false PCONFIG = false CET_IBT: CET indirect branch tracking = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa/eax): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) Architecture Performance Monitoring Features (0xa/ebx): core cycle event not available = false instruction retired event not available = false reference cycles event not available = false last-level cache ref event not available = false last-level cache miss event not avail = false branch inst retired event not available = false branch mispred retired event not avail = false Architecture Performance Monitoring Features (0xa/edx): number of fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) anythread deprecation = false XSAVE features (0xd/0): XCR0 lower 32 bits valid bit field mask = 0x00000007 XCR0 upper 32 bits valid bit field mask = 0x00000000 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = false XCR0 supported: AVX-512 ZMM_Hi256 = false XCR0 supported: AVX-512 Hi16_ZMM = false IA32_XSS supported: PT state = false XCR0 supported: PKRU state = false IA32_XSS supported: HDC state = false bytes required by fields in XCR0 = 0x00000340 (832) bytes required by XSAVE/XRSTOR area = 0x00000340 (832) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = true SAVE area size in bytes = 0x00000340 (832) IA32_XSS lower 32 bits valid bit field mask = 0x00000000 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false extended processor signature (0x80000001/eax): family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15) model = 0x1 (1) stepping id = 0x1 (1) extended family = 0x8 (8) extended model = 0x0 (0) (simple synth) = AMD Ryzen (Summit Ridge B1) [Zen], 14nm extended feature flags (0x80000001/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSCALL and SYSRET instructions = true memory type range registers = true global paging extension = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true multiprocessing capable = false no-execute page protection = true AMD multimedia instruction extensions = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true 1-GB large page support = true RDTSCP = true long mode (AA-64) = true 3DNow! instruction extensions = false 3DNow! instructions = false extended brand id (0x80000001/ebx): raw = 0x70000000 (1879048192) BrandId = 0x0 (0) AMD feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true CMP Legacy = true SVM: secure virtual machine = true extended APIC space = true AltMovCr8 = true LZCNT advanced bit manipulation = true SSE4A support = true misaligned SSE mode = true 3DNow! PREFETCH/PREFETCHW instructions = true OS visible workaround = true instruction based sampling = false XOP support = false SKINIT/STGI support = true watchdog timer support = true lightweight profiling support = false 4-operand FMA instruction = false TCE: translation cache extension = true NodeId MSR C001100C = false TBM support = false topology extensions = true core performance counter extensions = true data breakpoint extension = true performance time-stamp counter support = false performance counter extensions = true MWAITX/MONITORX supported = true brand = "AMD Ryzen Threadripper 1950X 16-Core Processor " L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x40 (64) instruction associativity = 0xff (255) data # entries = 0x40 (64) data associativity = 0xff (255) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x40 (64) instruction associativity = 0xff (255) data # entries = 0x40 (64) data associativity = 0xff (255) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x8 (8) size (KB) = 0x20 (32) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x4 (4) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x400 (1024) instruction associativity = 8-way (6) data # entries = 0x600 (1536) data associativity = 0x3 (3) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x400 (1024) instruction associativity = 8-way (6) data # entries = 0x600 (1536) data associativity = 0x5 (5) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 8-way (6) size (KB) = 0x200 (512) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 32-way (10) size (in 512KB units) = 0x40 (64) RAS Capability (0x80000007/ebx): MCA overflow recovery support = true SUCCOR support = true HWA: hardware assert support = false scalable MCA support = true Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio = 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode = true FID: frequency ID control = false VID: voltage ID control = false TTP: thermal trip = true TM: thermal monitor = true STC: software thermal control = false 100 MHz multiplier control = false hardware P-State control = true TscInvariant = true CPB: core performance boost = false read-only effective frequency interface = true processor feedback interface = false APM power reporting = false connected standby = true RAPL: running average power limit = true Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x30 (48) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction = true instructions retired count support = true always save/restore error pointers = true Logical CPU cores (0x80000008/ecx): number of CPU cores - 1 = 0x1f (31) ApicIdCoreIdSize = 0x5 (5) SVM Secure Virtual Machine (0x8000000a/eax): SvmRev: SVM revision = 0x1 (1) SVM Secure Virtual Machine (0x8000000a/edx): nested paging = true LBR virtualization = true SVM lock = true NRIP save = true MSR based TSC rate control = true VMCB clean bits support = true flush by ASID = true decode assists = true SSSE3/SSE5 opcode set disable = false pause intercept filter = true pause filter threshold = true AVIC: AMD virtual interrupt controller = true virtualized VMLOAD/VMSAVE = true virtualized GIF = true NASID: number of address space identifiers = 0x8000 (32768): L1 TLB information: 1G pages (0x80000019/eax): instruction # entries = 0x40 (64) instruction associativity = full (15) data # entries = 0x40 (64) data associativity = full (15) L2 TLB information: 1G pages (0x80000019/ebx): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) SVM Secure Virtual Machine (0x8000001a/eax): 128-bit SSE executed full-width = true MOVU* better than MOVL*/MOVH* = true 256-bit SSE executed full-width = false Instruction Based Sampling Identifiers (0x8000001b/eax): IBS feature flags valid = true IBS fetch sampling = true IBS execution sampling = true read write of op counter = true op counting mode = true branch target address reporting = true IbsOpCurCnt and IbsOpMaxCnt extend 7 = true invalid RIP indication support = true fused branch micro-op indication support = true IBS fetch control extended MSR support = true IBS op data 4 MSR support = false Lightweight Profiling Capabilities: Availability (0x8000001c/eax): lightweight profiling = false LWPVAL instruction = false instruction retired event = false branch retired event = false DC miss event = false core clocks not halted event = false core reference clocks not halted event = false interrupt on threshold overflow = false Lightweight Profiling Capabilities: Supported (0x8000001c/edx): lightweight profiling = false LWPVAL instruction = false instruction retired event = false branch retired event = false DC miss event = false core clocks not halted event = false core reference clocks not halted event = false interrupt on threshold overflow = false Lightweight Profiling Capabilities (0x8000001c/ebx): LWPCB byte size = 0x0 (0) event record byte size = 0x0 (0) maximum EventId = 0x0 (0) EventInterval1 field offset = 0x0 (0) Lightweight Profiling Capabilities (0x8000001c/ecx): latency counter bit size = 0x0 (0) data cache miss address valid = false amount cache latency is rounded = 0x0 (0) LWP implementation version = 0x0 (0) event ring buffer size in records = 0x0 (0) branch prediction filtering = false IP filtering = false cache level filtering = false cache latency filteing = false Cache Properties (0x8000001d): --- cache 0 --- type = data (1) level = 0x1 (1) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x3f (63) physical line partitions = 0x0 (0) number of ways = 0x7 (7) number of sets = 63 write-back invalidate = false cache inclusive of lower levels = false --- cache 1 --- type = instruction (2) level = 0x1 (1) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x3f (63) physical line partitions = 0x0 (0) number of ways = 0x3 (3) number of sets = 255 write-back invalidate = false cache inclusive of lower levels = false --- cache 2 --- type = unified (3) level = 0x2 (2) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x3f (63) physical line partitions = 0x0 (0) number of ways = 0x7 (7) number of sets = 1023 write-back invalidate = false cache inclusive of lower levels = true --- cache 3 --- type = unified (3) level = 0x3 (3) self-initializing = true fully associative = false extra cores sharing this cache = 0x7 (7) line size in bytes = 0x3f (63) physical line partitions = 0x0 (0) number of ways = 0xf (15) number of sets = 8191 write-back invalidate = true cache inclusive of lower levels = false extended APIC ID = 12 Extended APIC ID (0x8000001e/ebx): compute unit ID = 0x6 (6) cores per compute unit - 1 = 0x1 (1) Extended APIC ID (0x8000001e/ecx): node ID = 0x0 (0) nodes per processor = 2 nodes (1) SME/SEV (0x8000001f): SME: secure memory encryption support = true SEV: secure encrypted virtualize support = true MIN_SEV_ASID = 0x1 (1) MAX_SEV_ASID = 0xf (15) (instruction supported synth): CMPXCHG8B = true conditional move/compare = true PREFETCH/PREFETCHW = true (multi-processing synth): multi-core (c=32) (multi-processing method): AMD (APIC widths synth): CORE_width=5 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0 (synth) = AMD Ryzen (Summit Ridge B1) [Zen], 14nm Hope it helps, and ask for anything you may need. Thanks!
  4. HI; there you go: gdb 0ad/system/pyrogenesis_dbg >> run >> bt: #0 0x00007ffff594cd42 in waitpid () from /usr/lib/libpthread.so.0 #1 0x0000555555daa347 in try_gui_display_error ( text=0x7fff33d10000 L"Assertion failed: \"tlb.Validate()\"\r\nLocation: cache.cpp:54 (AddTLB)\r\n\r\nCall stack:\r\n\r\n(0x555555da8b91) /home/szz/0ad/0ad/binaries/system/pyrogenesis_dbg(+0x854b91) [0x555555da8b91]\n(0x555555d6ca63) /h"..., manual_break=true, allow_suppress=true, no_continue=false) at ../../../source/lib/sysdep/os/unix/unix.cpp:165 #2 0x0000555555daa558 in sys_display_error ( text=0x7fff33d10000 L"Assertion failed: \"tlb.Validate()\"\r\nLocation: cache.cpp:54 (AddTLB)\r\n\r\nCall stack:\r\n\r\n(0x555555da8b91) /home/szz/0ad/0ad/binaries/system/pyrogenesis_dbg(+0x854b91) [0x555555da8b91]\n(0x555555d6ca63) /h"..., flags=6) at ../../../source/lib/sysdep/os/unix/unix.cpp:215 #3 0x0000555555d6ccb2 in CallDisplayError ( text=0x7fff33d10000 L"Assertion failed: \"tlb.Validate()\"\r\nLocation: cache.cpp:54 (AddTLB)\r\n\r\nCall stack:\r\n\r\n(0x555555da8b91) /home/szz/0ad/0ad/binaries/system/pyrogenesis_dbg(+0x854b91) [0x555555da8b91]\n(0x555555d6ca63) /h"..., flags=6) at ../../../source/lib/debug.cpp:383 #4 0x0000555555d6d082 in debug_DisplayError (description=0x7fffffffb100 L"Assertion failed: \"tlb.Validate()\"", flags=6, context=0x7fffffffb740, lastFuncToSkip=0x5555571fe070 L"debug_OnAssertionFailure", pathname=0x555555f83158 L"../../../source/lib/sysdep/arch/x86_x64/cache.cpp", line=54, func=0x555555f83f39 <x86_x64::AddTLB(x86_x64::Cache const&)::__func__> "AddTLB", suppress=0x55555621ec28 <x86_x64::AddTLB(x86_x64::Cache const&)::suppress__>) at ../../../source/lib/debug.cpp:474 #5 0x0000555555d6d550 in debug_OnAssertionFailure (expr=0x555555f83268 L"tlb.Validate()", suppress=0x55555621ec28 <x86_x64::AddTLB(x86_x64::Cache const&)::suppress__>, file=0x555555f83158 L"../../../source/lib/sysdep/arch/x86_x64/cache.cpp", line=54, func=0x555555f83f39 <x86_x64::AddTLB(x86_x64::Cache const&)::__func__> "AddTLB") at ../../../source/lib/debug.cpp:563 #6 0x0000555555d9b1a3 in x86_x64::AddTLB (tlb=...) at ../../../source/lib/sysdep/arch/x86_x64/cache.cpp:54 #7 0x0000555555d9b7f2 in x86_x64::AMD::AddTLB2Pair (reg=1442866176, pageSize=4096) at ../../../source/lib/sysdep/arch/x86_x64/cache.cpp:172 #8 0x0000555555d9b9e8 in x86_x64::AMD::DetectCacheAndTLB () at ../../../source/lib/sysdep/arch/x86_x64/cache.cpp:203 #9 0x0000555555d9c1f3 in x86_x64::DetectCacheAndTLB () at ../../../source/lib/sysdep/arch/x86_x64/cache.cpp:623 #10 0x0000555555ded703 in ModuleInit (initState=0x55555621ec80 <x86_x64::Caches(unsigned long)::initState>, init=0x555555d9c144 <x86_x64::DetectCacheAndTLB()>) at ../../../source/lib/module_init.cpp:46 #11 0x0000555555d9c5a4 in x86_x64::Caches (idxCache=2) at ../../../source/lib/sysdep/arch/x86_x64/cache.cpp:652 #12 0x0000555555d9cf85 in topology::MaxLogicalPerCache () at ../../../source/lib/sysdep/arch/x86_x64/topology.cpp:116 #13 0x0000555555d9d764 in topology::DetermineCachesProcessorMask (cachesProcessorMask=0x55555621ef68 <topology::cacheTopology+520>, numCaches=@0x55555621ed60: 0) at ../../../source/lib/sysdep/arch/x86_x64/topology.cpp:392 #14 0x0000555555d9d9ce in topology::InitCacheTopology () at ../../../source/lib/sysdep/arch/x86_x64/topology.cpp:449 #15 0x0000555555ded703 in ModuleInit (initState=0x55555621f168 <topology::cacheInitState>, init=0x555555d9d991 <topology::InitCacheTopology()>) at ../../../source/lib/module_init.cpp:46 #16 0x0000555555d9da3b in topology::NumCaches () at ../../../source/lib/sysdep/arch/x86_x64/topology.cpp:456 #17 0x00005555559e961b in RunHardwareDetection () at ../../../source/ps/GameSetup/HWDetect.cpp:306 #18 0x00005555559d94ca in InitGraphics (args=..., flags=0, installedMods=std::vector of length 0, capacity 0) at ../../../source/ps/GameSetup/GameSetup.cpp:1001 #19 0x00005555556c5f75 in RunGameOrAtlas (argc=1, argv=0x7fffffffdfb8) at ../../../source/main.cpp:631 #20 0x00005555556c67d2 in main (argc=1, argv=0x7fffffffdfb8) at ../../../source/main.cpp:680 If there is anything more I can do please make me know! Thanks! Szz.
  5. HI everyone, I tried to install 0ad in archlinux, both from repos and compiling the game from source, and the game won't start, if I type 0ad in a terminal I get: TIMER| InitVfs: 1.4161 ms Writing the mainlog at /home/szz/.config/0ad/logs/mainlog.html TIMER| CONFIG_Init: 1.2561 ms Sound: AlcInit success, using OpenAL Soft TIMER| shutdown ConfigDB: 44.628 us TIMER| resource modules: 2.91112 ms TIMER TOTALS (9 clients) ----------------------------------------------------- tc_pool_alloc: 0 c (0x) tc_png_decode: 0 c (0x) tc_dds_transform: 0 c (0x) tc_transform: 0 c (0x) tc_plain_transform: 0 c (0x) tc_ShaderGLSLLink: 0 c (0x) tc_ShaderGLSLCompile: 0 c (0x) tc_ShaderValidation: 0 c (0x) xml_validation: 0 c (0x) ----------------------------------------------------- TIMER| shutdown misc: 177.746 us TIMER| InitVfs: 66.0578 ms Writing the mainlog at /home/szz/.config/0ad/logs/mainlog.html TIMER| CONFIG_Init: 971.702 us Sound: AlcInit success, using OpenAL Soft cache.cpp(54): Assertion failed: "tlb.Validate()" Assertion failed: "tlb.Validate()" Location: cache.cpp:54 (AddTLB) Call stack: (0x55ac8f75dbaf) /usr/bin/pyrogenesis(+0x610baf) [0x55ac8f75dbaf] (0x55ac8f708152) /usr/bin/pyrogenesis(+0x5bb152) [0x55ac8f708152] (0x55ac8f709682) /usr/bin/pyrogenesis(+0x5bc682) [0x55ac8f709682] (0x55ac8f709b9b) /usr/bin/pyrogenesis(+0x5bcb9b) [0x55ac8f709b9b] (0x55ac8f755eef) /usr/bin/pyrogenesis(+0x608eef) [0x55ac8f755eef] (0x55ac8f756213) /usr/bin/pyrogenesis(+0x609213) [0x55ac8f756213] (0x55ac8f7563f1) /usr/bin/pyrogenesis(+0x6093f1) [0x55ac8f7563f1] (0x55ac8f7568b5) /usr/bin/pyrogenesis(+0x6098b5) [0x55ac8f7568b5] (0x55ac8f78ca33) /usr/bin/pyrogenesis(+0x63fa33) [0x55ac8f78ca33] (0x55ac8f75710f) /usr/bin/pyrogenesis(+0x60a10f) [0x55ac8f75710f] (0x55ac8f757fdb) /usr/bin/pyrogenesis(+0x60afdb) [0x55ac8f757fdb] (0x55ac8f78ca33) /usr/bin/pyrogenesis(+0x63fa33) [0x55ac8f78ca33] (0x55ac8f757bab) /usr/bin/pyrogenesis(+0x60abab) [0x55ac8f757bab] (0x55ac8f3f9f7f) /usr/bin/pyrogenesis(+0x2acf7f) [0x55ac8f3f9f7f] (0x55ac8f3f08df) /usr/bin/pyrogenesis(+0x2a38df) [0x55ac8f3f08df] (0x55ac8f1fd085) /usr/bin/pyrogenesis(+0xb0085) [0x55ac8f1fd085] errno = 0 (Invalid alignment) OS error = ? (C)ontinue, (S)uppress, (B)reak, Launch (D)ebugger, or (E)xit? c cache.cpp(54): Assertion failed: "tlb.Validate()" Assertion failed: "tlb.Validate()" Location: cache.cpp:54 (AddTLB) Call stack: (0x55ac8f75dbaf) /usr/bin/pyrogenesis(+0x610baf) [0x55ac8f75dbaf] (0x55ac8f708152) /usr/bin/pyrogenesis(+0x5bb152) [0x55ac8f708152] (0x55ac8f709682) /usr/bin/pyrogenesis(+0x5bc682) [0x55ac8f709682] (0x55ac8f709b9b) /usr/bin/pyrogenesis(+0x5bcb9b) [0x55ac8f709b9b] (0x55ac8f755eef) /usr/bin/pyrogenesis(+0x608eef) [0x55ac8f755eef] (0x55ac8f756213) /usr/bin/pyrogenesis(+0x609213) [0x55ac8f756213] (0x55ac8f7563fe) /usr/bin/pyrogenesis(+0x6093fe) [0x55ac8f7563fe] (0x55ac8f7568b5) /usr/bin/pyrogenesis(+0x6098b5) [0x55ac8f7568b5] (0x55ac8f78ca33) /usr/bin/pyrogenesis(+0x63fa33) [0x55ac8f78ca33] (0x55ac8f75710f) /usr/bin/pyrogenesis(+0x60a10f) [0x55ac8f75710f] (0x55ac8f757fdb) /usr/bin/pyrogenesis(+0x60afdb) [0x55ac8f757fdb] (0x55ac8f78ca33) /usr/bin/pyrogenesis(+0x63fa33) [0x55ac8f78ca33] (0x55ac8f757bab) /usr/bin/pyrogenesis(+0x60abab) [0x55ac8f757bab] (0x55ac8f3f9f7f) /usr/bin/pyrogenesis(+0x2acf7f) [0x55ac8f3f9f7f] (0x55ac8f3f08df) /usr/bin/pyrogenesis(+0x2a38df) [0x55ac8f3f08df] (0x55ac8f1fd085) /usr/bin/pyrogenesis(+0xb0085) [0x55ac8f1fd085] errno = 0 (No error reported here) OS error = ? XIO: fatal IO error 2 (No such file or directory) on X server ":0" after 266 requests (266 known processed) with 28 events remaining. Is there anyway to fix this? Thanks in advance. P.D: related topic ==> https://forum.manjaro.org/t/0ad-cache-cpp-54-assertion-failed-tlb-validate/78421
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